Jumat, 20 Maret 2009

NEW Patent CD for Clock data recovery circuit with improved jitter transfer ...


NEW Patent CD for Clock data recovery circuit with improved jitter transfer ...



NEW Patent CD for Clock data recovery circuit with improved jitter transfer ...


Product Features

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  • Patent Search on CD Containing over 50 related Patents in PDF Format
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Product Description
Following is a sample of the information contained on this cd.. BACKGROUND OF THE INVENTION1. Technical Field of the InventionThe present invention relates to a clock data recovery circuit, more specifically, to a clock data recovery circuit to be used in SONET (Synchronous Optical Network)/SDH (Synchronous Digital Hierarchy) standards for optical communications networks.2. Description of the Related ArtThe American Synchronous Optical Network (SONET) was standardized in the mid 1980s by the American National Standards Institute (ANSI) to efficiently house a third group of circuits (45M bits/second) in optical fiber transmission lines and to form economical digital networks. Furthermore, Synchronous Digital Hierarchy (SDH) is synchronous digital hierarchy specifications standardized as ITU-T (International Telecommunication Union-Telecommunication Standardization Sector) in 1988 based on SONET to unify digital hierarchies different among Japan, the USA, and Europe, and this SDH has realized building of ATM (Asynchronous Transfer Mode) networks on a global level.Generally, a conventional clock data recovery circuit retimes an input signal by using a clock extracted from the input signal itself, and outputs this retimed signal and the extracted clock. In a clock data recovery circuit used in the SONET/SDH, both an extracted clock that is an output signal from the clock data recovery circuit and output data must have characteristics satisfying the SONET/SDH standards. Particularly, in a digital communications system, excessive jitter causes an unallowable BER (bit error rate), so that a clock extracted from the clock data recovery circuit and output data must have jitter transfer characteristics and jitter tolerance, both of which satisfy the SONET/SDH standards.FIG. 1 is a block diagram showing a general conventional clock data recovery circuit (Digest of Technical Papers, pp.251, FIG. 15.2.2, 2002 IEEE, International Solid-State Circuits Conference).

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